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1 si40 21 - ds rev 2.3r 0408 www.silabs.com/integration SI4021 universal ism band fsk transmitter description silicon labs SI4021 is a single chip, low power, multi - channel fsk transmitter designed for use in applications requiring fcc or etsi conformance for unlicensed use in the 433, 868, and 915 mhz bands. used in conjunction with si40 20, silicon labs fsk receiver, the SI4021 transmitter features ezradio tm technology, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. all required rf functions ar e integrated. only an external crystal and bypass filtering are needed for operation. the SI4021 builds on the features presented by the si40 20 by offering a higher output power and an improved phase noise characteristic. the SI4021 shares the same pinout and control command set as the si40 20 . the SI4021 offers all of the frequencies as the si40 20 , with the exception of the 315 mhz band. the SI4021 features a completely integrated pll for easy rf design, and its rapid settling time allows for fast frequen cy hopping, bypassing multipath fading and interference to achieve robust wireless links. in addition, highly stable and accurate fsk modulation is accomplished by direct closed - loop modulation with bit rates up to 115.2 kbps. the plls high resolution all ows the use of multiple channels in any of the bands. the integrated power amplifier of the transmitter has an open - collector differential output that directly drive a loop antenna with programmable output level. no additional matching network is required. an automatic antenna tuning circuit is built in to avoid costly trimming procedures and de - tuning due to the hand effect. for low - power applications, the device supports automatic activation from sleep mode. active mode can be initiated by several wake - up events (on - chip timer timeout, low supply voltage detection, or activation of any of the four push - button inputs). the SI4021 s on - chip digital interface supports both a microcontroller mode and an eeprom mode. the latter allows complete data transmit ter operation without a microcontroller (both control commands and data are read from the eeprom). any wake - up event can start a transmission of the corresponding data stored in the eeprom. functional block diagram SI4021 pin assignment microcontroller mode eeprom mode this document refers to SI4021 - ic rev a1 . see www.silabs.com/integration for any applicable errata. see back page f or ordering information. features ? fully integrated (low bom, easy design - in) ? no alignment required in production ? fast settling, programmable, high - resolution pll ? fast frequency hopping capability ? stable and accurate fsk modulation with programmable dev iation ? programmable pll loop bandwidth ? direct loop antenna drive ? automatic antenna tuning circuit ? programmable output power level ? alternative ook support ? eeprom mode supported ? spi bus for applications with microcontroller ? clock output for microcontroller ? integrated programmable crystal load capacitor ? multiple event handling options for wake - up activation ? push - button event handling with switch de - bounce ? wake - up timer ? low battery detection ? 2.2 to 5.4 v supply voltage ? low power consumption ? low standby current (0.3 a) ? compact 16 - pin tssop package ? transmit bit synchronization typical applications ? remote control ? home security and alarm ? wireless keyboard/mouse and other pc peripherals ? toy control ? remote keyless entry ? tire pressure monitoring ? telemetry ? personal/ patient data logging ? remote automatic meter reading crystal oscillator synthesizer low battery detect wake-up timer controller reference load cap low bat treshold timeout period clock frequency level rfp rfn nirq/nlbd clk/sdo sdi sck nsel fsk pb4 pb3 pb2 pb1 vss vdd mod xtl ook s d i s c k n s e l p b 1 p b 2 p b 3 p b 4 c l k f s k v d d n i r q r f p r f n m o d v s s x t l 1 2 4 5 3 6 7 8 1 6 1 5 1 3 1 2 1 4 1 1 1 0 9 s d i s c k n s e l p b 1 p b 2 p b 3 p b 4 s d o f s k v d d n l b d r f p r f n m o d v s s x t l 1 2 4 5 3 6 7 8 1 6 1 5 1 3 1 2 1 4 1 1 1 0 9
si 4 0 21 2 detailed description the SI4021 fsk transmitter is designed to cover the unlicensed frequency bands at 433, 868, and 915 mhz. the device facilitates compliance with fcc and etsi requirements. pll the pr ogrammable pll synthesizer determines the operating frequency, while preserving accuracy based on the on - chip crystal - controlled reference oscillator. the plls high resolution allows the usage of multiple channels in any of the bands. the fsk deviation is selectable (from 30 to 210 khz with 30 khz increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is also highly accurate due to the direct closed - loop modulation of the pll. the transmitted digital data can be sent asynchronously through the fsk pin or over the control interface using the appropriate command. the rf vco in the pll performs automatic calibration, which requires only a few microseconds. to ensure proper operation in the programmed frequency band, the rf vco is automatically calibrated upon activation of the synthesizer. if temperature or supply voltage change significantly or operational band has changed, vco recalibration is recommended.. recalibration can be initiated at any time by switching the synthesizer off and back on again. rf power amplifier (pa) the power amplifier has an open - collector differential output and can directly drive a loop antenna with a programmable output power level. an automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so - called hand effect. the transmitters can operate in on - off keying (ook) mode by switching the power amplifier on and off. when the appropriate control bit is set using the power setting command , the fsk pin becomes an enable input (active high) for the power amplifier. crystal oscillator the chip has a single - pin crystal oscillator circuit, which provides a 10 mhz reference signal for the pll. to reduce external parts and simplify design, the crystal load capacitor i s internal and programmable. guidelines for selecting the appropriate crystal can be found later in this datasheet. the transmitters can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. when the chip receives a sleep command from the microcontroller and turns itself off, it provides several further clock pulses (clock tail) for the microcontroller to be able to go to idle or sleep mode. the length of the clock tail is programmable. low battery voltage detector the low battery voltage detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. the detector circuit has 50 mv hysteresis. wake - up timer the wake - up timer has very l ow current consumption (1.5 a typical) and can be programmed from 1 ms to several days with an accuracy of 5%. it calibrates itself to the crystal oscillator at every startup, and then every 30 seconds. when the oscillator is switched off, the calibration circuit switches on the cr ystal oscillator only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake - up timing. the auto calibration feature can be disabled by setting the a bit in the low battery detector command . event handling in order to minimize current consumption, the device supports sleep mode. active mode can be initiated by several wake - up events: timeout of wake - up timer, detection of low supply voltage, pressing any of the four push - button inputs, or through the serial interface. the push - button inputs can be driven by a logic signal from a microcontroller or controlled directly by normally open switches. pull - up resistors are integrated. if any wake - up event occurs, the wake - up logic generates an interrupt, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. the cause of the interrupt can be read out from the transmitters by the microcontroller through the nirq pin. interface an spi compatible serial interface lets the user select the operating frequency band and center frequency of the synthesizer, polarity and deviation of fsk modulation, and output power level. division ratio for the microcontroller clock, wake - up timer period, and low battery detector threshold are also programmable. any of these auxiliary functions can be disabled when not needed. all parameters are set to default after power - on; the programmed values are retained during sleep mode. eeprom mode in simple applications, the on - chip digital controller provi des the transmitters with direct interface to a serial (spi) eeprom. in this case, no external microcontroller is necessary. wake - up events initiate automatic readout of the assigned command sequence from eeprom memory. for every event, there is a dedicate d starting address available in the eeprom. programming the eeprom is very simple. any control command can be programmed in the eeprom sequentially (same as in microcontroller mode). the internal power - on reset (por) is a dedicated event, which can be used to program the basic settings of the transmitters. in this case the chip starts to read out the preprogrammed data from the 00h address in eeprom. data can be transmitted with the help of the data transmit command , which tells the transmitters how many by tes must be transmitted. the whole process finishes with a sleep command.
si 4 0 21 3 package pin definiti ons , microcontroller mo de pin type key: d=digital, a=analog, s=supply, i=input, o=output, io=input/output microcontroller mode pin assignment pin name type function 1 sdi di data input of serial control interface 2 sck di clock input of serial control interface 3 nsel di chip select input of serial control interface (active low) 4 pb1 di push - button input #1 (active low with internal pull - up resisto r) 5 pb2 di push - button input #2 (active low with internal pull - up resistor) 6 pb3 di push - button input #3 (active low with internal pull - up resistor) 7 pb4 di push - button input #4 (active low with internal pull - up resistor) 8 clk do microcontrolle r clock (1 mhz - 10 mhz) 9 xtl aio crystal connection (other terminal of crystal to vss) 10 vss s ground reference 11 mod di connect to logic high (microcontroller mode) 12 rfn ao power amplifier output (open collector) 13 rfp ao power amplifier out put (open collector) 14 nirq do interrupt request output for microcontroller (active low) and status read output 15 vdd s positive supply voltage 16 fsk di serial data input for fsk modulation s d i s c k n s e l p b 1 p b 2 p b 3 p b 4 c l k f s k v d d n i r q r f p r f n m o d v s s x t l 1 2 4 5 3 6 7 8 1 6 1 5 1 3 1 2 1 4 1 1 1 0 9
si 4 0 21 4 typical application, microcontroller mode v d d x t l v s s m o d r f n r f p n i r q v d d f s k x 1 1 0 m h z g n d g n d g n d 1 1 6 2 1 5 3 1 4 4 1 3 5 1 2 6 1 1 7 1 0 8 9 i a 4 2 2 1 g n d c 3 1 0 p c 2 1 0 0 p c 1 1 u r 1 4 7 0 d 1 l e d r e d g p 4 g p 3 g p 2 g p 1 m i c r o c o n t r o l l e r g p 0 c l k i n ( e c o s c . m o d e ) s d i s c k n s e l p b 1 p b 2 p b 3 p b 4 c l k g p 5 o p t i o n a l s 1 s 2 s 3 s 4 o p t i o n a l g n d g p 6 g p 7 g p 8 g p 9 t o o t h e r c i r c u i t s a n t e n n a
si 4 0 21 5 package pin definiti ons, eeprom mode pin type key: d=digital, a=analog, s=supply, i=input, o=output, io=input/output eeprom mode pin assignment pin name type function 1 sdi di data input of serial control interface 2 sck do clock output of serial control interface 3 nsel do chip select output of serial control interface (active low) 4 pb1 di push - button input #1 (active low with internal pull - up resistor) 5 pb2 di push - button input #2 (active low with interna l pull - up resistor) 6 pb3 di push - button input #3 (active low with internal pull - up resistor) 7 pb4 di push - button input #4 (active low with internal pull - up resistor) 8 sdo do data output of serial control interface 9 xtl aio crystal c onnection (other terminal of crystal to vss) 10 vss s ground reference 11 mod di connect to logic low (eeprom mode) 12 rfn ao power amplifier output (open collector) 13 rfp ao power amplifier output (open collector) 14 nlbd do low battery voltage detector output (active low) 15 vdd s positive supply voltage 16 fsk di not used, connect to vdd or vss s d i s c k n s e l p b 1 p b 2 p b 3 p b 4 s d o f s k v d d n l b d r f p r f n m o d v s s x t l 1 2 4 5 3 6 7 8 1 6 1 5 1 3 1 2 1 4 1 1 1 0 9
si 4 0 21 6 typical application, eeprom mode v d d 1 8 3 7 2 6 4 5 e ep r o m 2 5 a a 08 0 1 1 6 2 1 5 3 1 4 4 1 3 5 1 2 6 1 1 7 1 0 8 9 i a 4 2 2 1 s d i s c k n s e l pb 1 pb 2 pb 3 pb 4 l t x 0 d s vs s m o d r f n r f p nl b d v d d f s k n c s s o n w p i s d n g s c k h o l d v c c r 1 4 7 0 d 1 l e d r e d x 1 10 m h z g n d g n d g n d g n d g n d s 1 s 2 s 3 s 4 c 3 1 0 p c 2 10 0 p c 1 1 u x a n t e n n a o p t i o n a l
si 4 0 21 7 general device specification s all voltages are referenced to v ss , the potential on the ground reference pin vss. absolute maximum ratings (non - operating) symbol parameter min max units v dd positive supply voltage - 0.5 6.0 v v in voltage on any pin except open collector outputs - 0.5 v dd +0.5 v v oc voltage on open collector outputs - 0. 5 6.0 v i in input current into any pin except vdd and vss - 25 25 ma esd electrostatic discharge with human body model 1000 v t st storage temperature - 55 125 o c t ld lead temperature (soldering, max 10 s) 260 o c recommended operating range sym bol parameter min max units v dd positive supply voltage 2.2 5.4 v v oc voltage on open collector outputs (max 6.0 v) v dd - 1 v dd + 1 v t op ambient operating temperature - 40 85 oc electrical specifica tion (min/max values are valid over the whole recomme nded operating range, typ ical conditions: t op = 27 o c; v dd = v oc = 2.7 v) dc characteristics symbol parameter conditions/notes min typ max units i dd_tx_0 supply current (tx mode, pout = 0 dbm) 433 mhz band 12 ma 868 mhz band 14 915 mhz band 1 5 i dd_tx_pmax supply current (tx mode, pout = p max ) 433 mhz band 21 ma 868 mhz band 23 915 mhz band 24 i pd standby current in sleep mode (note 1) all blocks disabled 0.3 a i wt wake - up timer current consumption 1.5 a i lb low b attery detector current consumption 0.5 a i x idle current only crystal oscillator is on 1.5 ma v lba low battery detection accuracy +/ - 3 % v lb low battery detector threshold programmable in 0.1 v steps 2.25 5.35 v v il digital input low l evel 0.3*v dd v v ih digital input high level 0.7*v dd v i il digital input current v il = 0 v - 1 1 a i ih digital input current v ih = v dd , v dd = 5.4 v - 1 1 a v ol digital output low level i ol = 2 ma 0.4 v v oh digital output high level i o h = - 2 ma v dd - 0.4 v note for table above is on page 7.
si 4 0 21 8 ac characteristics symbol parameter conditions/notes min typ max units f ref pll reference frequency crystal operation mode is parallel (note 2) 8 10 12 mhz f o transmitter frequency 433 mhz ban d, 2.5 khz resolution 430.24 439.75 868 mhz band, 5.0 khz resolution 860.48 879.51 915 mhz band, 7.5 khz resolution 900.72 929.27 t lock pll lock time frequency error < 10 khz after 10 mhz step, por default pll setting (note 7) 20 s t sp pll startup time after turning on from idle mode, with crystal oscillator already stable, por default pll setting (note 7) 250 s i out open collector output current (note 3) at all bands 0.5 6 ma p maxl available output power (433 mhz band) with opt. antenna impedance (note 4) 8 dbm p maxh available output power (868 and 915 mhz band) with opt. antenna impedance (note 4) 6 dbm p out typical output power selectable in 3 db steps (note 3) p max - 21 p max dbm p s p spurious emission at max power with loop antenna ( note 5) - 50 dbc c o output capacitance (set by the automatic antenna tuning circuit) at low bands 1.5 2.3 3.1 pf at high bands 1.6 2.2 2.8 q o quality factor of the output capacitance 16 1 8 22 l out output phase noise 100 khz from carrier - 85 dbc/hz 1 mhz from carrier (note 7) - 105 br fsk fsk bit rate (note 7) 115.2 kbps br ook ook bit rate 512 kbps df fsk fsk frequency deviation programmable in 30 khz steps 30 210 khz c xl crystal load capacitance programmable in 0.5 pf steps, tolerance +/ - 10% 8.5 16 pf see crystal selection guidelines t por internal por timeout (note 6) after v dd has reached 90% of final value 1 50 ms t sx crystal oscillator st artup time crystal esr < 100 ohms (note 8) 1.5 5 ms t pbt wake - up timer accuracy crystal oscillator must be enabled to ensure proper calibration at startup (note 8) +/ - 10 % t wake - up programmable wake - up time 1 5 10 11 ms c in, d digital in put capacitance 2 pf t r, f digital output rise/fall time 15 pf pure capacitive load 10 ns all n ote s for table above are on page 7.
si 4 0 21 9 note 1: using a cr2032 battery (225 mah capacity), the expected battery life is greater than 2 years usin g a 60 - second wake - up period for sending 100 byte packets in length at 19.2 kbps with +3 dbm output power in the 915 mhz band. note 2: using anything but a 10 mhz crystal is allowed but not recommended because all crystal - referred timing and frequency para meters will change accordingly. note 3: adjustable in 8 steps. note 4: optimal antenna admittance/impedance for the SI4021 : yantenna [s] zantenna [ohm] lantenna [nh] 434 mhz 1.3e - 3 - j6.3e - 3 31 + j152 58.00 868 mhz 1.35e - 3 - j1.2e - 2 9 + j82 15.20 91 5 mhz 1.45e - 3 - j1.3e - 2 8.7 + j77 13.60 note 5: with selective resonant antennas (see: application notes available from http:// www.silabs.com/integration ). note 6: during this period, no commands are accepted by the chip. for detailed information see t he reset modes section. note 7: the maximum fsk bitrate and the output phase noise are dependent on the on the actual setting of the pll setting command . note 8: the crystal oscillator start - up time strongly depends on the capacitance seen by the oscillat or. using low capacitance and low esr crystal is recommended. when designing the pcb layout keep the trace connecting to the crystal short to minimize stray capacitance.
si 4 0 21 10 typical performance data phase noise measurements in the 868 mhz ism band 50% charge pump current setting (ref. level: - 60 dbc/hz, 10 db/div) 100, 50, 33% charge pump current settings (ref. level: - 70 dbc/hz, 5 db/div) unmodulated rf spectrum the output spectrum is measured at different frequencies. the output is loaded with 50 ohms through a matching network. at 868 mhz at 915 mhz 1 1 : 5 2 : 4 7 m a y 5 , 2 0 0 5 p h a s e n o i s e l m a r k e r t r a c e t y p e x a x i s v a l u e 1 2 3 4 2 2 2 2 s p o t f r e q s p o t f r e q s p o t f r e q s p o t f r e q 1 0 k h z 1 5 1 k h z 1 m h z 5 . 0 0 8 m h z - 7 6 . 6 5 d b c / h z - 8 6 . 9 5 d b c / h z - 1 0 7 . 1 1 d b c / h z - 1 1 5 . 6 5 d b c / h z 1 0 k h z 1 0 m h z f r e q u e n c y o f f s e t c a r r i e r p o w e r a t t e n m k r r e f - 6 0 . 0 0 d b c / h z 1 0 . 0 0 d b / 1 2 3 4 - 1 1 . 1 1 d b m 0 . 0 0 d b 4 5 . 0 0 8 0 0 m h z - 1 1 5 . 6 5 d b c / h z 1 3 : 3 0 : 4 9 m a y 5 , 2 0 0 5 p h a s e n o i s e l m a r k e r t r a c e t y p e x a x i s v a l u e 1 2 3 1 2 3 s p o t f r e q s p o t f r e q s p o t f r e q 1 m h z 1 m h z 1 m h z - 1 0 1 . 9 5 d b c / h z - 1 0 7 . 0 5 d b c / h z - 1 0 9 . 9 8 d b c / h z 1 0 k h z 1 0 m h z f r e q u e n c y o f f s e t c a r r i e r p o w e r a t t e n m k r r e f - 7 0 . 0 0 d b c / h z 5 . 0 0 d b / 1 2 3 - 1 1 . 0 3 d b m 0 . 0 0 d b 1 1 . 0 0 0 0 0 m h z - 1 0 1 . 9 5 d b c / h z 1 0 : 2 6 : 5 0 m a y 5 , 2 0 0 5 l r e f 0 d b m a t t e n 1 0 d b m k r 1 8 6 8 . 0 0 1 0 m h z - 1 2 . 2 d b m s a m p l o g 1 0 d b / v a v g 1 0 0 w 1 s 2 s 3 f c a a c e n t e r 8 6 8 m h z r e s b w 1 0 k h z v b w 1 0 k h z s p a n 2 m h z s w e e p 4 0 . 7 4 m s ( 2 0 0 1 p t s ) 1 1 0 : 3 4 : 5 7 m a y 5 , 2 0 0 5 l r e f 0 d b m a t t e n 1 0 d b m k r 1 9 1 5 . 0 0 2 0 m h z - 1 4 . 0 9 d b m s a m p l o g 1 0 d b / v a v g 1 0 0 w 1 s 2 s 3 f c a a c e n t e r 9 1 5 m h z r e s b w 1 0 k h z v b w 1 0 k h z s p a n 2 m h z s w e e p 4 0 . 7 4 m s ( 2 0 0 1 p t s ) 1
si 4 0 21 11 modulated rf spectrum at 433 mhz with 180 khz deviation at 64 kbps at 868 mhz with 180 khz deviation at 64 kbps spurious rf spectrum with 10 mhz clk output enabled at 433 mhz antenna tuning characteristics 750 C 970 mhz the antenna tuning characteristics was recorded in max - hold state of the spectrum analyzer. during the measurement, the transmitters were forced to change frequencies by forcing an external reference signal to the xtl pi n. while the carrier was changing the antenna tuning circuit switched trough all the available states of the tuning circuit. the graph clearly demonstrates that while the complet e output circuit had about a 40 mhz bandwidth, the tuning allows operating in a 220 mhz band. in other words, the tuning circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread. 1 7 : 1 8 : 2 3 d e c 7 , 2 0 0 5 r e f 1 0 d b m a t t e n 2 0 d b m k r 1 ? 1 9 . 9 8 m h z - 4 4 . 2 3 d b # p e a k l o g 1 0 d b / v a v g 3 w 1 s 2 s 3 f c a a c e n t e r 4 3 4 m h z # r e s b w 3 k h z # v b w 3 0 0 h z s p a n 5 0 m h z s w e e p 4 5 . 4 7 s ( 2 0 0 0 p t s ) 1 1 r 1 7 : 1 1 : 4 1 d e c 7 , 2 0 0 5 r e f 1 0 d b m a t t e n 2 0 d b # s a m p l o g 1 0 d b / v a v g 2 4 w 1 s 2 s 3 f c a a c e n t e r 4 3 4 m h z # r e s b w 1 k h z # v b w 1 k h z s p a n 2 m h z s w e e p 4 . 0 7 4 s ( 2 0 0 0 p t s ) 1 7 : 2 6 : 1 7 d e c 7 , 2 0 0 5 r e f 1 0 d b m a t t e n 2 0 d b # s a m p l o g 1 0 d b / v a v g 5 0 w 1 s 2 s 3 f c a a c e n t e r 8 6 8 m h z # r e s b w 1 k h z # v b w 1 k h z s p a n 2 m h z s w e e p 4 . 0 7 4 s ( 2 0 0 0 p t s )
si 4 0 21 12 control interface commands to the transmitters are sent serially. data bits on pin sdi are shifted in to the device upon the rising edge of the clock on pin sck whenever the chip select pin nsel is low. when the nsel signal is high, it initializes the serial interface. the number of bi ts sent is an integer multiple of 8. all commands consist of a command c ode, followed by a varying number of parameter or data bits. all data are sent msb first (e.g. bit 15 for a 16 - bit command). bits having no influence (dont care) are indicated with x. the power on reset (por) circuit sets default values in all control and command registers. the status information or received data can be read serially over the irq pin. bits are shifted out upon the falling edge of clk signal timing specification symbol parameter minimum value [ns] t ch clock high time 25 t cl clock lo w time 25 t ss select setup time (nsel falling edge to sck rising edge) 10 t sh select hold time (sck falling edge to nsel rising edge) 10 t shi select high time 25 t ds data setup time (sdi transition to sck rising edge) 5 t dh data hold ti me (sck rising edge to sdi transition) 5 t od data delay time 10 t bl push - button input low time 25 timing diagram
si 4 0 21 13 control commands control command related parameters/functions related control bits 1 configuration setting command frequency band, microcontroller clock output, crystal load capacitance, frequency deviation b1 to b0, d2 to d0, x3 to x0, ms, m2 to m0 2 power management command crystal oscillator, synthesizer, power amplifier, low battery detector, wake - up timer, clock output bu ffer a1 a0, ex, es, ea, eb, et, dc 3 frequency setting command carrier frequency f11 to f0 4 data rate command bit rate r7 to r0 5 power setting command nominal output power, ook mode ook, p2 to p0 6 low battery detector command low battery threshold l imit, transmit bit synchronizer, wake - up timer calibration dwc, ebs, t4 to t0 7 sleep command length of the clock tail after power down s7 to s0 8 push - button command push - button related functions p4, d1 to d0, b4 to b1, bc 9 wake - up timer command wake - up time period r4 to r0, m7 to m0 10 data transmit command data transmission 11 status register command transmitter status read 12 pll setting and reset mode command pll bandwidth, reset mode bw1 to bw0, dr note : in the following tables the por colu mn shows the default values of the command registers after power - on. 1. configuration setting command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 0 0 b1 b0 d2 d1 d0 x3 x2 x1 x0 ms m2 m1 m0 8080h the resulting output frequency can be calculated as: f out = f 0 C ( - 1) sign * (m + 1) * (30 khz) where: f 0 is the channel center frequency (see the next command) m is the three bit binary number < m2 : m0> sign = ( ms ) xor (fsk i nput) note: ? use m in a range from 0 to 6. b1 b0 frequency band {mhz] 0 0 315 0 1 433 1 0 868 1 1 915 clock output frequency [mhz] 0 0 0 1 0 0 1 1.25 0 1 0 1.66 0 1 1 2 1 0 0 2.5 1 0 1 3.33 1 1 0 5 1 1 1 10 d2 d1 d0 x3 x2 x1 x0 crystal load capacitance [pf] 0 0 0 0 8.5 0 0 0 1 9.0 0 0 1 0 9.5 0 0 1 1 10.0 1 1 1 0 15.5 1 1 1 1 16.0
si 4 0 21 14 2. power management command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 0 0 0 a1 a0 ex es ea eb et dc c000h bits 5 - 0, enable the corresponding block of the transmitters, i.e. the crystal oscilla tor is enabled by the ex bit, the synthesizer by es , the power amplifier by ea and the low battery detector by eb , while the wake - up timer by et. the bit dc disables the clock output buffer. when receiving the data transmit command , the chip supports autom atic on/off control over the crystal oscillator, the pll and the pa. if bit a1 is set, the crystal oscillator and the synthesizer are controlled automatically. data transmit command starts up the crystal oscillator and as soon as a stable reference frequen cy is available the synthesizer starts. after a subsequent delay to allow locking of the pll, if a0 is set the power amplifier is turned on as well. note : ? to enable the automatic internal control of the crystal oscillator, the synthesizer and the power amp lifier, the corresponding bits ( ex, es, ea ) must be zero in the power management command . ? in microcontroller mode, the ex bit should be set in the power management command for the correct control of es and ea . the oscillator can be switched off by clearing the ex bit after the transmission. ? in eeprom operation mode after an identified data transmit command the internal logic switches on the synthesizer and pa. at the end of data transmit command header if necessary the current clock cycle is automatically e xtended to ensure the pll stabilization and rf power ramp - up. ? in eeprom operation mode the internal logic switches off the pa when the given number of bytes is transmitted. (see: data transmit command in eeprom operation.) ? when the chip is controlled by a microcontroller, the sleep command can be used to indicate the end of the data transmission process, because in microcontroller mode the data transmit command does not contain the length of the tx data. ? for processing the events caused by the peripheral bl ocks (por, lbd, wake - up timer, push - buttons) the chip requires operation of the crystal oscillator. this operation is fully controlled internally, independently from the status of the ex bit, but if the dc bit is zero, the oscillator remains active until s leep command is issued. (this command can be considered as an event controller reset.) oscillator control logic e x w a k e - u p t i m e r i n t . c a l . d c u c m o d e c l k r e q u e s t f r o m p e r i p h e r a l b l o k s e n a b l e o s c i l l a t o r ( p o r , w a k e - u p t i m e r , l b d , p b s ) s l e e p c o m m a n d d a t a t r a n s m i t c o m m a n d
si 4 0 21 15 3. frequency setting command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 a7d0h the 12 - bit parameter of the frequency setting command has the value f. the value f should be in the range of 96 and 3903. when f is out of range, the previous value is kept. the synthesizer center frequency f 0 can be calcula ted as: f 0 = 10 mhz * c1 * (c2 + f/4000) the constants c1 and c2 are determined by the selected band as: band [mhz] c1 c2 433 1 43 868 2 43 915 3 30 note: ? for correct operation of the frequency synthesizer, the frequency and band of operation nee d to be programmed before the synthesizer is started. directly after activation of the synthesizer, the rf vco is calibrated to ensure proper operation in the programmed frequency band. 4. data rate command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 1 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 c800h in eeprom mode the transmitted bit rate is determined by the 8 - bit value r (bits < r7 : r0>) as: br = 10 mhz / 29 / (r+1) apart from setting custom values, the standard bit rates from 2.4 to 115.2 kbps can b e approximated with minimal error. the commands are read out with a different fixed bit rate: f sck = 10 mhz / 29 / 3 [~115.2 khz] note: ? pll bandwidth should be set according the data rate. please see the pll setting command . 5. power setting command bi t 7 6 5 4 3 2 1 0 por 1 0 1 1 ook p2 p1 p0 b0h the bit ook enables the ook mode for the pa, in this case the data to be transmitted are received through the fsk pin. the output power is given in the table as relative to the maximum available power, which depends on the actual antenna impedance. (see: antenna application note available from www.silabs.com/integration ). p2 p1 p0 relative output pow er [db] 0 0 0 0 0 0 1 -3 0 1 0 -6 0 1 1 -9 1 0 0 -12 1 0 1 -15 1 1 0 -18 1 1 1 -21
si 4 0 21 16 6. low battery detector command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 0 1 0 dwc 0 eb s t4 t3 t2 t1 t0 c200h bit 7 disables the wake - up timer periodical (every 30 second) calibration if this bit is set. bit 5 enables the tx bit synchronization circuit. the data rate must be set by the data rate command. the 5 - bit value t of < t4 : t0> determines the threshold voltage v lb of the detector: v lb = 2.2 5 v + t * 0.1 v 7. sleep command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 c410h the effect of this command depends on the power management command . it immediately disables the power amplifier (if a0 =1 and ea =0) and the synthesizer (if a1 =1 and es =0). stops the crystal oscillator after s periods of the microcontroller clock (if a1 =1 and ex =0) to enable the micr ocontroller to execute all necessary commands before entering sleep mode itself. the 8 - bit value s is determined by bits < s7 : s0> . t x b i t 2 t x b i t n t x b i t 1 t x d a t a ( r f m o d u l a t o r i n p u t ) s p i c o m m a n d s ( n s e l , s c k , s d i ) f s k o r s d i n i r q p o w e r m a n e a = 1 b i t t i m e e a = 0 p o w e r m a n l b d & b s y n c e b s = 1 n i r q d a t a r a t e s e t t h e d r 1 . 6 u s t x b i t n - 1 t x b i t n t x b i t 1 / / / / / / / / / / / / n i r q
si 4 0 21 17 8. push - button command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 1 0 1 0 p4 d1 d0 b4 b3 b2 b1 bc ca00h if t he corresponding bit was set ( b1 - b4 ) the event remains active while the button is pressed. in eeprom mode, the chip is continuously performing the routine assigned to the push - button while it is pressed. in microcontroller mode, the chip continuously gener ates interrupts on nirq until the push - button is released. weak pull - up currents are switched off when bc is high. the d0, d1 bits set the de - bouncing time period: d1 d0 de - bouncing time [ms] 0 0 160 0 1 40 1 0 10 1 1 0 (bypassed) note : ? unti l the de - bouncing time has expired, the crystal oscillator remains switched on, independent of the status of the ex bit in the power management command . (because the circuit uses the crystal oscillator signal for timing.) ? if the p4 bit is set, the controll er performs the routine assigned to the fourth button when pb1 and pb2 are pressed down simultaneously. with the addition of this feature, there is a way to build a device that uses 3 buttons, but performs 4 funct ions. ? it is possible to detect multiple pre ssed push - buttons, in both modes. in eeprom mode the controller executes sequentially all the routines belonging to the pressed buttons.
si 4 0 21 18 simultaneously pressed push - button detect by microcontroller simplified block diagram of push - button 1 C 4 inputs vdd microcontroller mode spi nirq por (internal) push button input 2 push button input 1 por pb1 pb1 pb2 pb1 pb2 pb1 status rd status rd status rd status rd status rd status rd status rd pb_nirqdly* note: *pb_nirqdly is equal with the debounce time t o d i g i t a l g l i t c h f i l t e r f o r p u s h - b u t t o n 4 p u s h - b u t t o n 1 , 2 , 3 d q c l r e v e n t f l a g s l e e p c o m m a n d * s t a t . r e g . r e a d c o m m a n d * * c o u n t / s i n g l e v d d n o t e : * i n e e p r o m m o d e * * i n u c c o n t r o l l e d m o d e p u s h - b u t t o n 1 p u s h - b u t t o n 2 p u s h - b u t t o n 4 i n t e r n a l b l o c k e r s i g n a l t o p u s h - b u t t o n 1 a n d p u s h - b u t t o n 2 p 4 w e a k p u l l - u p e n a b l e / d i s a b l e v d d w i t h i n t e r n a l w e a k p u l l - u p p o r , l b d , w a k e u p t i m e r , p . b u t t o n s e v e n t f l a g s n o t i c e : o n l y o n e e v e n t i s s e r v i c e d s i m u l t a n e o u s l y t h e o t h e r s a r e p e n d i n g . d i g i t a l g l i t c h f i l t e r c l k c l r f o r p . b 1 , 2 b 1 , b 2 , b 3 b c
si 4 0 21 19 9. wake - up timer command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 e000h the wake - up time period can be calculated as: t wake - up = m * 2 r [ms] , where m is defined by the < m7 : m0> digital value and r is defined by the < r4 : r0> digital value. the value of r should be in the range of 0 and 23. the maximum achievable wake - up time period can be up to 24 days. note: ? f or continual operation the et bit should be cleared and set at t he end of every cycle. software reset: sending fe00h command to the chip triggers software reset. for more details see the reset modes section. 10. data transmit command in eeprom operation mode: bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 0 1 1 0 n7 n6 n5 n4 n3 n2 n1 n0 - - in microcontroller slave mode: bit 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 0 this command indicates that the following bitstream coming in via the serial interface is to be transmitted. in eeprom mode, the 8 - bit value n of bits < n7 : n0> contains the number of data bytes to follow. note : ? this command is not needed if the transmitters power management bits ( ex, es, ea ) are fully controlled by the microcontroller and tx data comes through the fsk pin. ? if the crystal oscillator wa s formerly switched off ( ex =0), the internal oscillator needs t sx time, to switch on. the actual value depends on the type of quartz crystal used. ? if the synthesizer was formerly switched off ( es =0), the internal pll needs t sp startup time. valid data can be transmitted only when the internal locking process is finished. ? in eeprom mode, before issuing the data transmit command , the power amplifier must be enabled, with the ea or a0 bit in the power management command . ? in eeprom mode, when n bytes have been read and transmitted the controller continues reading the eeprom and processing the data as control commands. this process stops after sleep command has been read from the eeprom.
si 4 0 21 20 data transmit sequence through the fsk pin d ata transmit sequence through the sdi pin note : ? do not send clk pulses with the tx data bits, otherwise they will be interpreted as commands. ? this mode is not spi compatible, therefore it is not recommended in microcontroller mode. ? if the crystal oscillator and the pll are running, the t sx +t sp delay is not needed. n s e l s c k s d i i n s t r u c t i o n i n t e r n a l o p e r a t i o n s a 0 , a 1 = 0 e x , e s , e a = 1 x t a l o s c . s t a b l e x t a l o s c s t a u s f s k t x d a t a s y n t h e s i z e r o n , p l l l o c k e d , p a r e a d y t o t r a n s m i t s y n t h e s i z e r / p l l / p a s t a t u s t s x * t s p * c 0 h 3 8 h d o n ' t c a r e p o w e r m a n a g e m e n t c o m m a n d n o t e : * s e e p a g e 6 f o r t h e t i m i n g v a l u e s n s e l s c k s d i i n s t r u c t i o n t x d a t a t r a n s m i t d a t a t s x + t s p * d a t a t r a n s m i t c o m m a n d n o t e : * s e e p a g e 6 f o r t h e t i m i n g v a l u e s c 6 h
si 4 0 21 21 11. status register read command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 - - with this command, it is possible to read the chips status register through the nirq pin. this command clears the last serviced interrupt and processing the next pending one will start (if there is any). status register read sequence 12. pll setting and reset mode command bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 por 1 1 0 1 0 0 1 0 bw1 bw0 0 0 0 0 dr 0 d200h bits 7 - 6 < bw1 : bw0> select the pll bandwidth : bw1 bw0 max datarate [kbps] phase noise at 1mhz offset [dbc/hz] (typical) charge pump current 0 1 19.2 - 112 25% 1 1 38.4 - 110 33% 0 0 68.9 - 107 50% 1 0 115.2 - 102 100% bit 1 ( dr ): disables the highly sensitive reset mode. if this bit is cleared, a 600 mv glitch in the power supply may cause a system rese t. for more detailed description see the reset modes section. nsel sck sdi nirq 0 instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 por pb1 pb2 pb3 pb4 lbd wk-up nirq status out
si 4 0 21 22 eeprom mode in this mode , the transmitters can operate with a standard at least 1 kbyte serial eeprom with an spi interface, and no microcontroller i s necessary. the following events cause wake - up of the device: event number n eeprom entry point description 0 0000h power - on 1 0 080h low level on input pb1 2 0100h low level on input pb2 3 0180h low level on input pb3 4 0200h low level on input pb4 5 0280h low supply voltage level 6 0300h wake - up timer timeout after any of these events, the crystal oscillator turns on and t he device starts to read bytes from the eeprom continuously (block read) starting from address n * 128 (decimal) and executes them as commands as described in the previous section. note : zero bytes can be put in the eeprom for timing purposes. never put m ore than 31 consecutive zero bytes into the eeproms active region (between the actual entry point and the closing sleep command ). example eeprom hexa content power - on reset: 00000000 c0 c4 ca 1e c8 23 c4 00 00 00 00 00 00 00 00 00 00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 short explanation: data in address, command, and parameter fields are hexadecimal values. for the detailed description of the con trol command bits, see previous section. address command parameter related control command remarks 00 C 01 c0 c4 power management crystal C synthesizer C power amplifier auto on/off mode enable 02 C 03 ca 1e push button continuous execution for all push butto ns 04 C 05 c8 23 bit rate br=10m/29/(35+1)~9600 bps 06 - 07 c4 00 sleep power down
si 4 0 21 23 push - button 1: 00000080 88 72 a6 10 c6 60 55 55 55 55 55 55 55 55 55 55 00000090 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000a0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000b0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000c0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000d0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 000000e0 55 55 55 55 55 55 c4 00 00 00 00 00 00 00 00 00 000000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 short explanation: address command parameter related control command remarks 80 C 81 8 872 configuration control 433mhz band, xtal c l =12pf f dev =90khz 82 C 83 a 610 frequency f c =(43+1552/4000)*10mhz 84 C 85 c6 60 data transmit transmit the next 96 bytes 86 C e5 60x55 data e6 C e7 c4 00 sleep power down, go to address 80 note: this routine is repeatedly executed while pb1 is pressed, because continuous execution was selected at por (ca1e code issued in the power - on reset section before). rx - tx alignment procedu res rx - tx frequency offset can be caused only by the differences in the actual reference frequency. to minimize these errors it is s uggested to use the same crystal type and the same pcb layout for the crys tal placement on the rx and tx pcbs. to verify the possible rx - tx offset it is suggested to measure the clk output of both chips with a high level of accuracy. do not measure the output at the xtl pin since the measurement process itself will change the re ference frequency. since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the tx and rx side the re should be no offset if the clk signals have identical frequencies. it is possible to monitor the actual rx - tx offset using the afc status report included in the status byte of the receiver. by reading out the status byte from the receiver the actual measured offset frequency will be reported. in order to get accurate valu es the afc has to be disabled during the read by clearing the "en" bit in the afc control command (bit 0).
si 4 0 21 24 crystal selection gu idelines the crystal oscillator of the SI4021 requires a 10 mhz parallel mode crystal. the circuit contains an integrated load c apacitor in order to minimize the external component count. the internal load capacitance value is programmable from 8.5 pf to 16 pf in 0.5 pf ste ps. with appropriate pcb layout, the total load capacitance value can be 10 pf to 20 pf so a variety of crysta l types can be used. when the total load capacitance is not more than 20 pf and a worst case 7 pf shunt capacitance (c 0 ) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 100 ohms esr (equivalent series loss resistance). however, lower c 0 and esr values guarantee faster oscillator startup. it is recommended to keep the pcb parasitic capacitances on the xtl pin as low as possible. the crystal frequency is used as the reference of the pll, which generates the rf carrier frequency (f c ). therefore f c is directly proportional to the crystal frequency. the accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable carrier frequency error. maximu m xtal tolerances including temperature and aging [ppm] whenever a low frequency error is essential for the application, it is possible to pull the crystal to the accurate frequen cy by changing the load capacitor value. the wid est pulling range can be achieved if the nominal required load capacitance of the crystal is in the midrange, for example 16 pf. the pull - ability of the crystal is defined by its motional capacitance and c 0 . note: ? there may be other requirements for th e tx carrier accuracy with regards to the requirements as defined by standards and/or channel separations. bit rate: 2.4 kbps 30 60 90 120 150 180 210 433 mhz 20 50 75 100 100 100 100 868 mhz 10 25 40 60 75 100 100 915 mhz 10 25 40 50 75 75 100 bit rate: 9.6 kbps 30 60 90 120 150 180 210 433 mhz 15 50 75 100 100 100 100 868 mhz 8 25 40 60 75 75 100 915 mhz 8 25 40 50 70 75 100 bit rate: 38.4 kbps 30 60 90 120 150 180 210 433 mhz don't use 20 50 75 100 100 100 868 mhz don't use 10 30 40 60 75 100 915 mhz don't use 10 25 40 60 75 75 bit rate: 115.2 kbps 30 60 90 120 150 180 210 433 mhz don't use don't use don't use don't use 30 50 100 868 mhz don't use don't use don't use don't use 20 30 50 915 mhz don't use don't use don't use don't use 15 30 50 transmitter deviation [+/- khz] transmitter deviation [+/- khz] transmitter deviation [+/- khz] transmitter deviation [+/- khz]
si 4 0 21 25 reset modes the chip will enter into reset mode if any of the following conditions are met: ? power - on reset: during a power up sequence until the v dd has reached the correct level and stabilized ? power glitch reset: transients present on the v dd line ? software reset: special control command received by the chip power - on reset after power up the supply voltage starts to rise from 0v. the reset block has an internal ramping voltage reference (reset - ramp signal), which is rising at 100mv/ms (typical) rate. the chip remains in reset state while the voltage difference between the actual v dd and the internal reset - ramp signal is higher than the reset threshold voltage, which is 600 mv (typical). as long as the v dd voltage is less than 1.6v (typical) the chip stays in reset mode regardless the voltage difference between the v dd and the internal ramp signal. the reset event can last up to 150ms supposing that the v dd reaches 90% its final value within 1ms. during this period the chip does not accept control commands via the serial control interface. power - on reset example: power glitch reset the internal reset block has two basic mode of operation: normal and sensitive reset. the default mode is sensitive, which can be changed by the appropriate control command (see related control commands at the end of this section). in normal mode the power glitch detection circuit is disabled. ther e can be spikes or glitches on the v dd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high. in such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the v dd has a rising rate greater than 100mv/ms and the voltage difference between the internal ramp signal and the v dd reaches the reset threshold voltage (600 mv). typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. if for some reason the sensitive r eset cannot be disabled step - by - step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem. any negative change in the supply voltage will not cause reset event unless the v dd level reaches the reset threshold voltage (250mv in normal mode, 1.6v in sensitive reset mode). if the sensitive mode is disabled and the power supply turned off the v dd must drop below 250mv in order to trigger a power - on reset event when the supply voltage is turned back on. if the decoupling capacitors keep their charges for a long time it could happen that no reset will be generated upon power - up because the power glitch detector circuit is disabled. note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again. t i m e v d d r e s e t t h r e s h o l d v o l t a g e ( 6 0 0 m v ) n r e s o u t p u t h l 1 . 6 v i t s t a y s i n r e s e t b e c a u s e t h e v d d < 1 . 6 v ( e v e n i f t h e v o l t a g e d i f f e r e n c e i s s m a l l e r t h a n t h e r e s e t t h r e s h o l d ) r e s e t r a m p l i n e ( 1 0 0 m v / m s )
si 4 0 21 26 sensitive reset enabled, ripple on v dd : sensitive reset disabled: software reset software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. th e result of the command is the same as if power - on reset was occurred. v dd line filtering during the reset event (caused by power - on, fast positive spike on the supply line or software reset command) it is very important to keep the v dd line as smooth as possible. noise or periodic disturbi ng signal superimposed the supply voltage may prevent the part getting out from reset state. to avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing sig nal below 10mv p - p in the dc C 50khz range for 200ms from v dd ramp start.. typical example when a switch - mode regulator is used to supply the radio, switching noise may be present on the v dd line. follow the manufacturers recommendations how to decrease the ripple of the regulator ic and/or how to shift th e switching frequency. related control commands pll setting and reset mode command setting bit<1> to high will change the reset mode to normal from the default sensitive. sw reset command issuing fe00h command will trigger software reset. see the wake - up timer command . time v dd reset threshold voltage ( 600 mv ) nres output h l 1 . 6 v reset ramp line ( 100 mv / ms ) time v dd reset threshold voltage ( 600 mv ) nres output h l 250 mv reset ramp line ( 100 mv / ms )
si 4 0 21 27 simplified internal control and timing the internal controller uses the clock generated by the crystal oscillator to sequentially process the various events and to de - bounce the push - button (pb) inputs. if the oscillator is not running, internal logic automatically turns it on temporarily and then off again. such events are: any wake - up event (por, pb press, wake - up timer timeout and low supply voltage detection), pb release and status read request by the microcontroller. if two wake - up e vents occur in succession, the crystal oscillator stays on until the next status read (acknowledgment of the first event). simplified internal control and timing diagrams no t e : * tsx : crystal oscillator st a r tup t i m e ** length of tclk_tail is determined by the parameter in the sleep comm a n d v d d push-button inpu t x microcontrolle r mod e ( ec = 0, ex = 0 ) sp i osc_on (in t e r na l ) p o r ( i nte r na l ) debouncing time + t s x * status r d c m d status r d c m d (pb x ) stat. b i t s v d d sp i osc_on (in t e r na l ) p o r ( i nte r na l ) nirq status r d c m d (po r ) stat. b i t s status r d c m d (pb x ) stat. b i t s microcontroller mode w i th mu l t i p le e v e nt r ea d ( ec = 0, ex = 0 ) nirq push-button inpu t x 1u s tsx* (po r ) stat. b i t s tsx* tsx* v d d microcontrolle r mod e ( ec = 1, ex = 0 ) sp i osc_on (in t e r na l ) p o r ( i nte r na l ) slee p c m d slee p c m d push-button inpu t x tcl k _ta il * * status rd status rd tcl k _tail* *
si 4 0 21 28 matching network for a 50 ohm single ende d output matching network schematic si 4021 l1 [nh] l2 [nh] l3 [nh] l4 [nh] c1 [pf] (note 1) c1 [pf] (note 2) c2 [pf] c3 [pf] c4 [pf] (note 3) 433 mhz 16 47 390 16 3.3 3.3 6.0 2.7 220 868 mhz 5.1 24 100 5.1 2 1.5 2.2 1.2 47 915 mhz 4.3 24 100 4.3 2 1.8 2.2 1.2 33 note 1: 1 mm thick board note 2: 1.5 mm thick board note 3: c4 must be connected parallel to the supply decoupling capacitors (10nf + 2.2f recommended) as close as possible to the vdd and vss pins
si 4 0 21 29 example applications : data packet transm ission data packet structure an example data packet structure using the ia422x C ia4320 pair for data transmission. this packet structure is an example of how to use the high efficiency fifo mode at the receiver side: the first 3 bytes compose a 24 bit length 01 pattern to let enough time fo r the clock recovery of the receiver to lock. the next two bytes compose a 16 bit synchron pattern which is essential for the receivers fifo to find the byte synchron in the received bit st ream. the synchron patters is followed by the payload. the first b yte transmitted after the synchron pattern (d 0 in the picture above) will be the first received byte in the fifo. important: the bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the re ceiver side will be unable to track. further details of packet structures can be found in the ia ism - ugsb1 software development kit manual. aa aa aa 2d d4 databytes (received in the fifo of the receiver) preamble synchron pattern d 0 d 1 d 2 . . . d n
si 4 0 21 30 example applications for microcontroller mode schematic pcb layout of keyboard transmitter demo circuit using microcontroller mod e (operating in the 915 mhz band) top layer bottom layer i a422 1
si 4 0 21 31 for eeprom mode schematic pcb layout of push - button transmitter demo circuit using eeprom mode (operating in the 434 mhz band) top layer bottom layer
si 4 0 21 32 package information 16 - pin tssop d e t a i l a g au g e p l a n e 0 . 2 5 s e c t i o n b - b s e e d e t a i l a m i n . n o m . m ax . m i n . n o m . m ax . 7 4 0 , 0 0 2 , 1 a 6 0 0 , 0 2 0 0 , 0 5 1 , 0 5 0 , 0 1 a a 2 0 , 8 0 0 , 9 0 1 , 0 5 0 , 03 1 0 , 03 5 0 , 04 1 2 1 0 , 0 7 0 0 , 0 0 3 , 0 9 1 , 0 b b 1 0 , 1 9 0 , 2 2 0 , 2 5 0 , 00 7 0 , 00 9 0 , 01 0 8 0 0 , 0 4 0 0 , 0 0 2 , 0 9 0 , 0 c 6 0 0 , 0 4 0 0 , 0 6 1 , 0 9 0 , 0 1 c d 4 , 9 0 5 , 0 0 5 , 1 0 0 , 19 3 0 , 19 7 0 , 20 1 e e e 1 4 , 3 0 4 , 4 0 4 , 5 0 0 , 16 9 0 , 17 3 0 , 17 7 l 0 , 5 0 0 , 6 0 0 , 7 5 0 , 02 0 0 , 02 4 0 , 03 0 l 1 4 0 0 , 0 9 0 , 0 r 4 0 0 , 0 9 0 , 0 1 r 8 0 8 0 1 2 3 s y mbo l d i m e n s i o n s in m m d i m e n s io n s in in c h e s . c s b 6 2 0 . 0 . c s b 5 6 . 0 6 . 40 bs c . 12 r e f . 12 r e f . 12 r e f . 12 r e f . 1 . 00 r e f . 0 . 252 bs c . 0 . 39 r e f .
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si 4 0 21 34 related products and documents SI4021 universal ism band fsk transmitter description ordering number SI4021 16 - pin tssop SI4021 - ic cc16 rev a1 die see silicon labs demo boards and devel opment kits description ordering number development kit ia ism C dk remote temp. monitoring station ia ism C da td related resources description ordering number antenna selection guide ia ism C an1 antenna development guide ia ism C an2 ia4320 un iversal ism band fsk receiver s ee www.silabs.com/integration for details note: volume orders must include chip revision to be accepted. silicon labs, inc. 400 west cesar chavez austin, texas 78701 tel: 512.416.8500 fax: 512.416.9669 toll free: 877.444 .3032 www.silabs.com /integration wireless @silabs.com the specifications and descriptions in this document are based on information available at the time of publication and are subject to change without notice. silicon laboratories assumes no responsibilit y for errors or omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. sili con laboratories reserves the right to make changes to the product and its documentation at any time. silicon laboratories makes no representations, warranties, or guarantees regarding the suitability of its products for any particular purpose and does n ot assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability for consequential or incidental damages arising out of use or failure of the product. nothing in this document shall o perate as an express or implied license or indemnity under the intellectual property rights of silicon laboratories or third parties. the products described in this document are not intended for use in implantation or other direct life support application s where malfunction may result in the direct physical harm or injury to persons. no warranties of any kind, including but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . ?2008 sil icon laboratories, inc. all rights reserved. silicon laboratories is a trademark of silicon laboratories, inc. all other trademarks belong to their respective owners.
http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are not designed or authorized for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? and others are trademarks or registered trademarks of silicon laborato - ries inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders.

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